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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-50301-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM
CMOS
64 M (x16) FLASH MEMORY & x 16 M (x16) Mobile FCRAMTM x
MB84VD23381EF-85
s FEATURES
* Power Supply Voltage of 2.7 V to 3.0 V for FCRAM * Power Supply Voltage of 2.7 V to 3.3 V for Flash * High Performance 85 ns maximum access time (Flash) 85 ns maximum access time (FCRAM)
(Continued)
s PRODUCT LINE UP
Flash Memory VCCf = 2.7 V to 3.3 V Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) 85 85 35 FCRAM* VCCs = 2.7 V to 3.0 V 85 85 60
* : Both VCCf and VCCs must be the same level when either part is being accessed and VCCf can be 2.4 V during standby state.
s PACKAGE
101-ball plastic FBGA
(BGA-101P-M01)
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MB84VD23381EF-85
(Continued) * Operating Temperature -30 C to +85 C * Package 101-ball FBGA
- FLASH MEMORY * Simultaneous Read/Write Operations (FlexBankTM) Two virtual Banks are chosen from the combination of four physical banks Host system can program or erase in one bank, then read immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program * Minimum 100,000 Write/Erase Cycles * Sector Erase Architecture Sixteen 4 K words and one hundred twenty-six 32 K word sectors. Any combination of sectors can be concurrently erased. Also supports full chip erase. * Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready-Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic Sleep Mode When addresses remain stable, automatically switch themselves to low power mode. * Low VCC Write Inhibit 2.5 V * Hidden ROM (Hi-ROM) Region 256 byte of Hi-ROM, accessible through a new "Hi-ROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * WP/ACC Input Pin At VIL, allows protection of "outermost" 2 x 8 K bytes on both ends of boot secctors, regardless of sector protection/unprotection status. At VIH, allows removal of boot sector protection At VACC, program time will be reduced by 40 %. * Program Suspend/Resume Suspends the program operation to allow a read in another byte * Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device * Please refer to "MBM29DL640E" datasheet in detailed function - FCRAMTM * Power Dissipation Operating : 20 mA Max Standby : 100 A Max Power Down : 10 A Max * Power Down Control by CE2s * Byte Write Control : LBs (DQ7-DQ0) , UBs (DQ15-DQ8)
FlexBankTM is a trademark of Fujitsu Limited, Japan. FCRAMTMTM is a trademark of Fujitsu Limited, Japan. 2
MB84VD23381EF-85
s PIN ASSIGNMENT
FBGA (TOP VIEW) Marking side
A12 N.C. A11 N.C. A10 N.C. B12 N.C. B11 N.C. B10 N.C. C12 N.C. C11 N.C. C10 N.C. D9 A11 D8 A8 C7 N.C. C6 N.C. D7 WE D6 E10 A15 E9 A12 E8 A19 E7 CE2s E6 F10 A21 F9 A13 F8 A9 F7 A20 F6 RY/BY F5 A18 F4 A5 F3 A2 G5 A17 G4 A4 G3 A1 G2 N.C. H5 DQ1 H4 VSS H3 A0 H2 N.C. G11 N.C. G10 N.C. G9 A14 G8 A10 H11 N.C. H10 A16 H9 N.C. H8 DQ6 J10 VCCf J9 DQ15 J8 DQ13 J7 DQ4 J6 DQ3 J5 DQ9 J4 OE J3 CEf K10 VSS K9 DQ7 K8 DQ12 K7 VCCs K6 VCCf K5 DQ10 K4 DQ0 K3 CE1s L9 DQ14 L8 DQ5 L7 N.C. L6 DQ11 L5 DQ2 L4 DQ8 M3 N.C. M2 N.C. M1 N.C. N3 N.C. N2 N.C. N1 N.C. P3 N.C. P2 N.C. P1 N.C. M7 N.C. M6 N.C. M12 N.C. M11 N.C. M10 N.C. N12 N.C. N11 N.C. N10 N.C. P12 N.C. P11 N.C. P10 N.C.
WP/ACC RESET D5 LBs D4 A7 E5 UBs E4 A6 E3 A3 D2 N.C.
A3 N.C. A2 N.C. A1 N.C.
B3 N.C. B2 N.C. B1 N.C.
C3 N.C. C2 N.C. C1 N.C.
(BGA-101P-M01)
3
MB84VD23381EF-85
s PIN DESCRIPTION
Pin Configuration Pin A19 to A0 A21, A20 DQ15 to DQ0 CEf CE1s CE2s OE WE RY/BY UBs LBs RESET WP/ACC N.C. VSS VCCf VCCs Address Inputs (Common) Address Input (Flash) Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (FCRAM) Chip Enable (FCRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Outputs (Flash) Open Drain Output Upper Byte Control (FCRAM) Lower Byte Control (FCRAM) Hardware Reset Pin/Sector Protection Unlock (Flash) Write Protect/Acceleration (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (FCRAM) Function Input/Output I I I/O I I I I I O I I I I Power Power Power
4
MB84VD23381EF-85
s BLOCK DIAGRAM
VCCf A21 to A0 A21 to A0 VSS
RY/BY
WP/ACC RESET CEf
64 M bit Flash Memory DQ15 to DQ0
DQ15 to DQ0 VCCs A19 to A0 DQ15 to DQ0 VSS
LBs UBs WE OE CE1s CE2s
16 M bit FCRAM
5
MB84VD23381EF-85
s DEVICE BUS OPERATIONS
User Bus Operations Operation*1, *2 Full Standby Output Disable*3 Read from Flash*4 Write to Flash Read from FCRAM*5 Write to FCRAM Temporary Sector Group Unprotection*6 Flash Hardware Reset Boot Block Sector Write Protection FCRAM Power Down CEf CE1s CE2s OE H H L L L H H H L H H H L L X H H H H H H X H H L H L H WE LBs UBs DQ7 to DQ0 DQ15 to DQ8 RESET X H H H L H L X X X X X X L H L X X X X X X X X X X X X L L H X High-Z High-Z High-Z DOUT DIN DOUT DIN High-Z DIN X High-Z High-Z High-Z DOUT DIN DOUT DIN DIN High-Z X VID X H X H H H H H WP/ ACC*5 X X X X X
X X X
H X L
H X L
X X X
X X X
X X X
X X X
High-Z X X
High-Z X X
L X X
X L X
Legend : L = VIL, H = VIH, X = VIL or VIH. See "s DC CHARACTERISTICS" for voltage levels. *1 : Other operations not indicated in this column are prohibited. *2 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once. *3 : FCRAM Output Disable condition should not be kept longer than 1 s. *4 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *5 : FCRAM Byte control at Read operation is not supported. *6 : Also used for the extended sector group protections. Note : Protect "outermost" 2 x 8 K bytes (4 words) on both ends of the boot block sectors.
6
MB84VD23381EF-85
s FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
* Sixteen 4 K words, and one hundred twenty-six 32 K words. * Individual-sector, multiple sector, or bulk-erase capability.
SA0 : 8 KB (4 KW) SA1 : 8 KB (4 KW) SA2 : 8 KB (4 KW) SA3 : 8 KB (4 KW) SA4 : 8 KB (4 KW) SA5 : 8 KB (4 KW) SA6 : 8 KB (4 KW) SA7 : 8 KB (4 KW) SA8 : 64 KB (32 KW) SA9 : 64 KB (32 KW) SA10 : 64 KB (32 KW) SA11 : 64 KB (32 KW) SA12 : 64 KB (32 KW) SA13 : 64 KB (32 KW) SA14 : 64 KB (32 KW) SA15 : 64 KB (32 KW) SA16 : 64 KB (32 KW) SA17 : 64 KB (32 KW) SA18 : 64 KB (32 KW) SA19 : 64 KB (32 KW) SA20 : 64 KB (32 KW) SA21 : 64 KB (32 KW) SA22 : 64 KB (32 KW) SA23 : 64 KB (32 KW) SA24 : 64 KB (32 KW) SA25 : 64 KB (32 KW) SA26 : 64 KB (32 KW) SA27 : 64 KB (32 KW) SA28 : 64 KB (32 KW) SA29 : 64 KB (32 KW) SA30 : 64 KB (32 KW) SA31 : 64 KB (32 KW) SA32 : 64 KB (32 KW) SA33 : 64 KB (32 KW) SA34 : 64 KB (32 KW) SA35 : 64 KB (32 KW) SA36 : 64 KB (32 KW) SA37 : 64 KB (32 KW) SA38 : 64 KB (32 KW) SA39 : 64 KB (32 KW) SA40 : 64 KB (32 KW) SA41 : 64 KB (32 KW) SA42 : 64 KB (32 KW) SA43 : 64 KB (32 KW) SA44 : 64 KB (32 KW) SA45 : 64 KB (32 KW) SA46 : 64 KB (32 KW) SA47 : 64 KB (32 KW) SA48 : 64 KB (32 KW) SA49 : 64 KB (32 KW) SA50 : 64 KB (32 KW) SA51 : 64 KB (32 KW) SA52 : 64 KB (32 KW) SA53 : 64 KB (32 KW) SA54 : 64 KB (32 KW) SA55 : 64 KB (32 KW) SA56 : 64 KB (32 KW) SA57 : 64 KB (32 KW) SA58 : 64 KB (32 KW) SA59 : 64 KB (32 KW) SA60 : 64 KB (32 KW) SA61 : 64 KB (32 KW) SA62 : 64 KB (32 KW) SA63 : 64 KB (32 KW) SA64 : 64 KB (32 KW) SA65 : 64 KB (32 KW) SA66 : 64 KB (32 KW) SA67 : 64 KB (32 KW) SA68 : 64 KB (32 KW) SA69 : 64 KB (32 KW) SA70 : 64 KB (32 KW) 000000h 001000h 002000h 003000h 004000h 005000h 006000h 007000h 008000h 010000h 018000h 020000h 028000h 030000h 038000h 040000h 048000h 050000h 058000h 060000h 068000h 070000h 078000h 080000h 088000h 090000h 098000h 0A0000h 0A8000h 0B0000h 0B8000h 0C0000h 0C8000h 0D0000h 0D8000h 0E0000h 0E8000h 0F0000h 0F8000h 100000h 108000h 110000h 118000h 120000h 128000h 130000h 138000h 140000h 148000h 150000h 158000h 160000h 168000h 170000h 178000h 180000h 188000h 190000h 198000h 1A0000h 1A8000h 1B0000h 1B8000h 1C0000h 1C8000h 1D0000h 1D8000h 1E0000h 1E8000h 1F0000h 1F8000h 1FFFFFh SA71 : 64 KB (32 KW) SA72 : 64 KB (32 KW) SA73 : 64 KB (32 KW) SA74 : 64 KB (32 KW) SA75 : 64 KB (32 KW) SA76 : 64 KB (32 KW) SA77 : 64 KB (32 KW) SA78 : 64 KB (32 KW) SA79 : 64 KB (32 KW) SA80 : 64 KB (32 KW) SA81 : 64 KB (32 KW) SA82 : 64 KB (32 KW) SA83 : 64 KB (32 KW) SA84 : 64 KB (32 KW) SA85 : 64 KB (32 KW) SA86 : 64 KB (32 KW) SA87 : 64 KB (32 KW) SA88 : 64 KB (32 KW) SA89 : 64 KB (32 KW) SA90 : 64 KB (32 KW) SA91 : 64 KB (32 KW) SA92 : 64 KB (32 KW) SA93 : 64 KB (32 KW) SA94 : 64 KB (32 KW) SA95 : 64 KB (32 KW) SA96 : 64 KB (32 KW) SA97 : 64 KB (32 KW) SA98 : 64 KB (32 KW) SA99 : 64 KB (32 KW) SA100 : 64 KB (32 KW) SA101 : 64 KB (32 KW) SA102 : 64 KB (32 KW) SA103 : 64 KB (32 KW) SA104 : 64 KB (32 KW) SA105 : 64 KB (32 KW) SA106 : 64 KB (32 KW) SA107 : 64 KB (32 KW) SA108 : 64 KB (32 KW) SA109 : 64 KB (32 KW) SA110 : 64 KB (32 KW) SA111 : 64 KB (32 KW) SA112 : 64 KB (32 KW) SA113 : 64 KB (32 KW) SA114 : 64 KB (32 KW) SA115 : 64 KB (32 KW) SA116 : 64 KB (32 KW) SA117 : 64 KB (32 KW) SA118 : 64 KB (32 KW) SA119 : 64 KB (32 KW) SA120 : 64 KB (32 KW) SA121 : 64 KB (32 KW) SA122 : 64 KB (32 KW) SA123 : 64 KB (32 KW) SA124 : 64 KB (32 KW) SA125 : 64 KB (32 KW) SA126 : 64 KB (32 KW) SA127 : 64 KB (32 KW) SA128 : 64 KB (32 KW) SA129 : 64 KB (32 KW) SA130 : 64 KB (32 KW) SA131 : 64 KB (32 KW) SA132 : 64 KB (32 KW) SA133 : 64 KB (32 KW) SA134 : 8 KB (4 KW) SA135 : 8 KB (4 KW) SA136 : 8 KB (4 KW) SA137 : 8 KB (4 KW) SA138 : 8 KB (4 KW) SA139 : 8 KB (4 KW) SA140 : 8 KB (4 KW) SA141 : 8 KB (4 KW) 200000h 208000h 210000h 218000h 220000h 228000h 230000h 238000h 240000h 248000h 250000h 258000h 260000h 268000h 270000h 278000h 280000h 288000h 290000h 298000h 2A0000h 2A8000h 2B0000h 2B8000h 2C0000h 2C8000h 2D0000h 2D8000h 2E0000h 2E8000h 2F0000h 2F8000h 300000h 308000h 310000h 318000h 320000h 328000h 330000h 338000h 340000h 348000h 350000h 358000h 360000h 368000h 370000h 378000h 380000h 388000h 390000h 398000h 3A0000h 3A8000h 3B0000h 3B8000h 3C0000h 3C8000h 3D0000h 3D8000h 3E0000h 3E8000h 3F0000h 3F8000h 3F9000h 3FA000h 3FB000h 3FC000h 3FD000h 3FE000h 3FF000h 3FFFFFh
Bank A
Bank C
Bank B
Bank D
MB84VD23381EF Sector Architecture
7
MB84VD23381EF-85
Example of Virtual Banks Combination Bank 1 Bank Splits Mega bits 8 M bits 16 Mbits 24 Mbits 32 Mbits Combination of Memory Bank Sectors 8 K byte/ 64 K byte/ 4 K word 32 K word 8 15 Mega bits 56 Mbits 48 Mbits 40 Mbits 32 Mbits Bank 2 Combination of Memory Bank Bank B Bank C Bank D Bank B Bank C Bank A Bank C Bank D Bank C Bank D Sectors 8 K byte/ 64 K byte/ 4 K word 32 K word 8 111
1
Bank A Bank A Bank D Bank B Bank A Bank B
2
16
30
0
96
3
0
48
16
78
4
8
63
8
63
BankA : Address 000000h to 07FFFFh BankB : Address 080000h to 1FFFFFh BankC : Address 200000h to 37FFFFh BankD : Address 380000h to 3FFFFFh Sector Address Tables Sector Address Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 Bank A SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 Bank Address A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 A17 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 A16 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 A15 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 A14 0 0 0 0 1 1 1 1 X X X X X X X X A13 0 0 1 1 0 0 1 1 X X X X X X X X A12 0 1 0 1 0 1 0 1 X X X X X X X X 000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh Address Range
(Continued)
8
MB84VD23381EF-85
Sector Address Bank Sector SA16 SA17 SA18 Bank A SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 Bank B SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 Bank Address A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 A18 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 A17 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 A16 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A15 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh Address Range
(Continued)
9
MB84VD23381EF-85
Sector Address Bank Sector SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 Bank B SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 Bank C SA76 SA77 SA78 SA79 SA80 SA81 Bank Address A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 A19 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 A18 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 A17 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 A16 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1FFFFFh 200000h to 207FFFh 208000h to 20FFFFh 210000h to 217FFFh 218000h to 21FFFFh 220000h to 227FFFh 228000h to 22FFFFh 230000h to 237FFFh 238000h to 23FFFFh 240000h to 247FFFh 248000h to 24FFFFh 250000h to 257FFFh Address Range
(Continued)
10
MB84VD23381EF-85
Sector Address Bank Sector SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 Bank C SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 Bank Address A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 A18 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 A17 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 A16 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 258000h to 25FFFFh 260000h to 267FFFh 268000h to 26FFFFh 270000h to 277FFFh 278000h to 27FFFFh 280000h to 287FFFh 288000h to 28FFFFh 290000h to 297FFFh 298000h to 29FFFFh 2A0000h to 2A7FFFh 2A8000h to 2AFFFFh 2B0000h to 2B7FFFh 2B8000h to 2BFFFFh 2C0000h to 2C7FFFh 2C8000h to 2CFFFFh 2D0000h to 2D7FFFh 2D8000h to 2DFFFFh 2E0000h to 2E7FFFh 2E8000h to 2EFFFFh 2F0000h to 2F7FFFh 2F8000h to 2FFFFFh 300000h to 307FFFh 308000h to 30FFFFh 310000h to 317FFFh 318000h to 31FFFFh 320000h to 327FFFh 328000h to 32FFFFh 330000h to 337FFFh 338000h to 33FFFFh 340000h to 347FFFh 348000h to 34FFFFh 350000h to 357FFFh 358000h to 35FFFFh Address Range
(Continued)
11
MB84VD23381EF-85
(Continued)
Sector Address Bank Sector SA115 Bank C SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 Bank D SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 Bank Address A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A17 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 A14 X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 A13 X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 A12 X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 360000h to 367FFFh 368000h to 36FFFFh 370000h to 377FFFh 378000h to 37FFFFh 380000h to 387FFFh 388000h to 38FFFFh 390000h to 397FFFh 398000h to 39FFFFh 3A0000h to 3A7FFFh 3A8000h to 3AFFFFh 3B0000h to 3B7FFFh 3B8000h to 3BFFFFh 3C0000h to 3C7FFFh 3C8000h to 3CFFFFh 3D0000h to 3D7FFFh 3D8000h to 3DFFFFh 3E0000h to 3E7FFFh 3E8000h to 3EFFFFh 3F0000h to 3F7FFFh 3F8000h to 3F8FFFh 3F9000h to 3F9FFFh 3FA000h to 3FAFFFh 3FB000h to 3FBFFFh 3FC000h to 3FCFFFh 3FD000h to 3FDFFFh 3FE000h to 3FEFFFh 3FF000h to 3FFFFFh Address Range
12
MB84VD23381EF-85
Sector Group Addresses (MB84VD23381EF) Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 SGA25 SGA26 SGA27 SGA28 SGA29 SGA30 SGA31 SGA32 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 A19 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 A18 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 A17 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A16 0 0 0 0 0 0 0 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X X X X A15 0 0 0 0 0 0 0 0 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA24 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 SA67 to SA70 SA71 to SA74 SA75 to SA78 SA79 to SA82 SA83 to SA86 SA87 to SA90 SA91 to SA94 SA95 to SA98 SA99 to SA102 SA103 to SA106 X X X SA8 to SA10 A14 0 0 0 0 1 1 1 1 A13 0 0 1 1 0 0 1 1 A12 0 1 0 1 0 1 0 1 Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7
(Continued) 13
MB84VD23381EF-85
(Continued) Sector Group
SGA33 SGA34 SGA35 SGA36 SGA37 SGA38 SGA39 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47
A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A19 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
A18 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1
A17 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1
A16 X X X X X X 0 0 1 1 1 1 1 1 1 1 1
A15 X X X X X X 0 1 0 1 1 1 1 1 1 1 1
A14 X X X X X X X 0 0 0 0 1 1 1 1
A13 X X X X X X X 0 0 1 1 0 0 1 1
A12 X X X X X X X 0 1 0 1 0 1 0 1
Sectors SA107 to SA110 SA111 to SA114 SA115 to SA118 SA119 to SA122 SA123 to SA126 SA127 to SA130 SA131 to SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
Flash Memory Autoselect Codes Type Manufacture's Code Device Code Extended Device Code Sector Group Protection A21 to A12 BA*2 BA*
2 2
A6 VIL VIL VIL VIL VIL
A3 VIL VIL VIH VIH VIL
A2 VIL VIL VIH VIH VIL
A1 VIL VIL VIH VIH VIH
A0 VIL VIH VIL VIH VIL
Code (HEX) 04h 227Eh 2202h 2201h 01h*1
BA*
BA*2 Sector Group Addresses
*1 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2 : BA is Bank Address which is needed only in Command Autoselect mode.
14
MB84VD23381EF-85
Flash Memory Command Definitions Command Sequence Read/Reset* Read/Reset* Autoselect Program Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume Program Suspend Program Resume Set to Fast Mode Fast Program *2 Reset from Fast Mode*2 Extended Sector Group Protection *3 Query *4 Hi-ROM Entry Hi-ROM Program *5 Hi-ROM Exit *5
1 1
Bus First Bus Second Bus Write Write Cycle Write Cycle Cycles Req'd Addr. Data Addr. Data 1 3 3 4 6 6 1 1 1 1 3 2 2 XXXh F0h 55h 55h 55h 55h 55h 55h PD 555h AAh 2AAh 555h AAh 2AAh 555h AAh 2AAh 555h AAh 2AAh 555h AAh 2AAh BA BA BA BA B0h 30h B0h 30h
Third Bus Write Cycle Addr. 555h (BA) 555h 555h 555h 555h 555h SPA 555h
Fourth Bus Fifth Bus Sixth Bus Read/Write Write Cycle Write Cycle Cycle RA PA 555h 555h SPA RD PD 55h 55h 555h SA 10h 30h
Data Addr. Data Addr. Data Addr. Data F0h 90h A0h 80h 80h 20h 40h 88h
AAh 2AAh AAh 2AAh SD PD
555h AAh 2AAh XXXh A0h BA PA
90h XXXh F0h *6
4
XXXh 60h (BA) 55h
SPA
60h 55h
1 3
98h
555h AAh 2AAh
4
555h AAh 2AAh
55h
555h (HRBA) 555h
A0h (HRA) PA 90h XXXh
4
555h AAh 2AAh
55h
00h
(Continued)
15
MB84VD23381EF-85
(Continued)
*1 : Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. *2 : This command is valid during Fast Mode. *3 : This command is valid while RESET = VID. *4 : The valid addresses are A6 to A0. *5 : This command is valid during Hi-ROM mode. *6 : The data "00h" is also acceptable. Notes : * Address bits A21 to A11 = X = "H" or "L" for all address commands except for Program Address (PA) , Sector Address (SA) , and Bank Address (BA) . * Bus operations are defined in "User Bus Operation" in "s DEVICE BUS OPERATIONS". * RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank address (A21 to A19) * RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse. * SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) . SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. * HRA = Address of the Hi-ROM area (000000h to 00007Fh) * HRBA = Bank Address of the Hi-ROM area (A21 = A20 = A19 = VIL) * The system should generate the following address patterns: 555h or 2AAh to addresses (A10 to A0) . * Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. * The Command combinations not described in "Flash Memory Command Definitions" table are illegal.
16
MB84VD23381EF-85
s ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins*1 VCCf Supply*1, *2 VCCs Supply* RESET* *
1, 3 1
Symbol Tstg TA VIN VOUT VCCf VCCs VIN VACC
Rating Min -55 -30 -0.3 -0.3 -0.2 -0.2 -0.5 -0.5 Max +125 +85 VCCf + 0.3 VCCs + 0.3 +3.6 +3.3 +13.0 +10.5
Unit C C V V V V V V
WP/ACC*1, *4
*1 : Voltage is defined on the basis of VSS = GND = 0 V. *2 : Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to -1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCs + 0.3 V. During voltage transitions, input or I/O pins may overshoot to VCCf + 1.0 V or VCCs + 1.0 V for periods of up to 5 ns. *3 : Minimum DC input voltage on RESET pin is -0.5 V. During voltage transitions, RESET pin may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed 9.0 V. Maximum DC input voltage on RESET pin is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *4 : Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +10.5 V for periods of up to 20 ns, When VCCf is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Ambient Temperature VCCf Supply Voltages VCCs Supply Voltages Symbol TA VCCf VCCs Value Min -30 +2.7 +2.7 Max +85 +3.3 +3.0 Unit C V V
Notes : * Voltage is defined on the basis of VSS = GND = 0 V. * Operating ranges define those limits between which the functionality of the device is guaranteed. * VCCs can be 2.4 V minimum during standby state. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 17
MB84VD23381EF-85
s DC CHARACTERISTICS
Parameter Input Leakage Current Output Leakage Current RESET Inputs Leakage Current Flash VCC Active Current (Read) *1 Flash VCC Active Current (Program/Erase) *2 Flash VCC Active Current (Read-While-Program) *5 Flash VCC Active Current (Read-While-Erase) *5 Flash VCC Active Current (Erase-Suspend-Program) Symbol ILI ILO ILIT ICC1f ICC2f ICC3f ICC4f ICC5f Test Conditions VIN = VSS to VCC, VCC = VCC Max VOUT = VSS to VCC, VCC = VCC Max VCC = VCC Max, RESET = 12.5 V CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH VCCs = VCCs Max, tRC/tWC = Min CE1s = VIL, CE2s = VIH, VIN = VIH or VIL, tRC/tWC = Max IOUT = 0 mA VCCf = VCC Max, CEf = VCCf 0.3 V RESET = VCCf 0.3 V, WP/ACC = VCCf 0.3 V VCCf = VCC Max, RESET = VSS 0.3 V, WP/ACC = VCCf 0.3 V VCCf = VCC Max, CEf = VSS 0.3 V RESET = VCCf 0.3 V, WP/ACC = VCCf 0.3 V VIN = VCCf 0.3 V or VSS 0.3 V VCCs = VCCs Max, CE1s VCCs - 0.2 V, CE2s VCCs - 0.2V, VIN 0.2 V or VCCs - 0.2 V VCCs = VCCs Max, VIN VCCf - 0.2 V or VIN 0.2 V CE1s 0.2V, CE2s 0.2V, IOUT = 0 mA tCYCLE = 5 MHz tCYCLE = 1 MHz Value Min -1.0 -1.0 Typ 15 2.5 Max +1.0 +1.0 35 18 7 40 58 58 40 20 3.0 mA Unit A A A mA mA mA mA mA mA
FCRAM VCC Active Current
ICC1s
Flash VCC Standby Current Flash VCC Standby Current (RESET) Flash VCC Current (Automatic Sleep Mode) *3
ISB1f

1
5
A A
ISB2f
1
5
ISB3f
1
5
A
FCRAM VCC Standby Current
ISBs
80
100
A
FCRAM VCC Power Down Current
IPDs
10
A
(Continued)
18
MB84VD23381EF-85
(Continued)
Parameter Input Low Level Input High Level Voltage for Autoselect and Sector Protection (RESET) *4 Voltage for WP/ACC Sector Protection/Unprotection and Program Acceleration FCRAM Output Low Level FCRAM Output High Level Flash Output Low Level Flash Output High Level Low VCC Lock-Out Voltage Symbol VIL VIH VID VCCs = VCCs Min, IOL = 1.0 mA VCCs = VCCs Min, IOH = -0.5 mA VCCf = VCCf Min, IOL = 4.0 mA Test Conditions Flash FCRAM Value Min -0.3 2.0 2.3 11.5 Typ 9.0 Max 0.4 VCC + 0.3 12.5 Unit V V V
VACC VOL VOH VOL VOH VLKO
8.5 1.8 2.3
9.5 0.4 0.45 2.5
V V V V V V
VCCf = VCCf Min, IOH = -0.1 mA VCCf - 0.4
*1 : The ICC current listed includes both the DC operating current and the frequency dependent component. *2 : ICC active while Embedded Algorithm (program or erase) is in progress. *3 : Automatic sleep mode enables the low power mode when the address remains stable for 150 ns. *4 : Applicable for only VCC applying. *5 : Embedded Algorithm (program or erase) is in progress. (@5 MHz)
19
MB84VD23381EF-85
s AC CHARACTERISTICS
* CE Timing Parameter CE Recover Time CE Hold Time * Timing Diagram for alternating FCRAM to Flash Symbol JEDEC Standard tCCR tCHOLD Test Setup Value Min 0 3 Unit ns ns
CEf
tCCR
tCCR
CE1s
WE
tCHOLD tCHOLD
tCCR
tCCR
CE2s
20
MB84VD23381EF-85
* Read Only Operations Characteristics (Flash) Parameter Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CEf or OE, Whichever Occurs First RESET Pin Low to Read Mode CEf Switching Low or High Symbol JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Standard tRC tACC tCE tOE tDF tDF tOH tREADY tELFL tELFH Test Setup CEf = VIL OE = VIL OE = VIL -85 Min 85 0 Max 85 85 35 30 30 20 5 Unit ns ns ns ns ns ns ns s ns
Test Conditions : Output Load : 1 TTL gate and 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V or VCCf Timing measurement reference level Input : 0.5 x VCCf Output : 0.5 x VCCf
21
MB84VD23381EF-85
* Read Cycle (Flash)
tRC Address Stable
Address
tACC
CEf
tOE tDF
OE
tOEH
WE
tCE High-Z Output Valid tOH High-Z
Outputs
* Hardware Reset/Read Operation Timing Diagram (Flash)
tRC
Address
tACC
Address Stable
CEf
tRP
tRH
tRH
tCE
RESET
tOH High-Z
Outputs
Output Valid
22
MB84VD23381EF-85
* Erase/Program Operations (Flash) Parameter Write Cycle Time Address Setup Time (WE to Addr.) Address Setup Time to CEf Low During Toggle Bit Polling Address Hold Time (WE to Addr.) Address Hold Time from CEf or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Hold Time Read Toggle and Data Polling Symbol JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tGHEL tGHWL tWLEL tELWL tEHWH tWHEH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2
2
Value -85 Min 85 0 15 45 0 35 0 0 10 20 20 0 0 0 0 0 0 35 35 30 30 50 4 500 500 0 500 200 50 Typ 16 1 Max 85 90 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s ns ns ns ns ns ns ns s s 23 Unit
Standard tWC tAS tASO tAH tAHT tDS tDH tOEH tCEPH tOEPH tGHEL tGHWL tWS tCS tWH tCH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVLHT tVIDR tVACCR tRB tRP tEOE tRH tBUSY tTOW tSPD
CEf High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write (OE to CEf) Read Recover Time Before Write (OE to WE) WE Setup Time (CEf to WE) CEf Setup Time (WE to CEf) WE Hold Time (CEf to WE) CEf Hold Time (WE to CEf) Write Pulse Width CEf Pulse Width Write Pulse Width High CEf Pulse Width High Word Programming Operation Sector Erase Operation*1 VCCf Setup Time Voltage Transition Time* Rise Time to VID*
2

4
Rise Time to VACC Recover Time from RY/BY RESET Pulse Width Delay Time from Embedded Output Enable RESET High Level Period Before Read Program/Erase Valid to RY/BY Delay Erase Time-out Time*
3
Erase Suspend Transition Time*
MB84VD23381EF-85
*1 : Does not include the preprogramming time. *2 : For Sector Group Protection Operation. *3 : The time between writes must be less than "tTOW" otherwise that command will not be accepted and erasure will start. A time-out or "tTOW" from the rising edge of last CEf or WE whichever happens first will initiate the execution of the Sector Erase command (s) . *4 : When the Erase Suspend command is written during the Sector Erase operation, the device will take maximum of "tSPD" to suspend the erase operation.
24
MB84VD23381EF-85
* Write Cycle (WE control) (Flash)
3rd Bus Cycle
Data Polling PA tAS tAH PA tRC
Address
555h tWC
CEf
tCS tCH tCE
OE
tGHWL tWP tWPH tWHWH1 tOE
WE
tDS tDH tDF tOH
DQ
A0h
PD
DQ7
DOUT
DOUT
Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at word address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates the last two bus cycles out of four bus cycle sequence.
25
MB84VD23381EF-85
* Write Cycle (CEf control) (Flash)
3rd Bus Cycle
Data Polling PA tAS tAH PA
Address
555h tWC
WE
tWS tWH
OE
tGHEL tCP tCPH tWHWH1
CEf
tDS tDH
DQ
A0h
PD
DQ7
DOUT
Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at word address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates the last two bus cycles out of four bus cycle sequence.
26
MB84VD23381EF-85
* AC Waveforms Chip/Sector Erase Operations (Flash)
Address
555h tWC
2AAh tAS tAH
555h
555h
2AAh
SA*
CEf
tCS tCH
OE
tGHWL tWP tWPH
WE
tDS tDH AAh 55h 80h AAh 55h 30h for Sector Erase 10h
Data
tVCS
VCCf
* : SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.
27
MB84VD23381EF-85
* AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tCH
tOE
tDF
OE
tOEH
WE
tCE *
DQ7
Data
DQ7
DQ7 = Valid Data
High-Z
tWHWH1 or 2
DQ6 to DQ0
Data tBUSY
DQ6 to DQ0 = Output Flag tEOE
DQ6 to DQ0 Valid Data
High-Z
RY/BY
* : DQ7 = Valid Data (the device has completed the Embedded operation) .
28
MB84VD23381EF-85
* AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Address
tAHT tASO tAHT tAS
CEf
tCEPH
WE
tOEH tOEPH tOEH
OE
tDH tOE Toggle Data tBUSY Toggle Data tCE * Toggle Data Stop Toggling Output Valid
DQ6/DQ2
Data
RY/BY
* : DQ6 stops toggling (the device has completed the Embedded operation) .
29
MB84VD23381EF-85
* Bank-to-Bank Read/Write Timing Diagram (Flash)
Read tRC Command tWC BA2 (555h) tAS tAH Read tRC BA1 tACC tAS tCE tAHT Command tWC BA2 (PA) Read tRC BA1 Read tRC BA2 (PA)
Address
BA1
CEf
tOE tCEPH
OE
tGHWL tWP tOEH tDF
WE
tDS tDH tDF
DQ
Valid Output
Valid Intput (A0h)
Valid Output
Valid Intput (PD)
Valid Output
Status
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1 : Address corresponding to Bank 1. BA2 : Address corresponding to Bank 2.
30
MB84VD23381EF-85
* RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
Rising edge of the last WE signal
WE
Entire programming or erase operations
RY/BY
tBUSY
* RY/BY Timing Diagram during Write/Erase Operations (Flash)
WE
RESET
tRP tRB
RY/BY
tREADY
31
MB84VD23381EF-85
* Temporary Sector Group Unprotection (Flash)
VCCf
tVCS
tVIDR tVLHT
VID VIH RESET CE
WE
tVLHT tVLHT Program or Erase Command Sequence
RY/BY
Unprotection Period
* Acceleration Mode Timing Diagram (Flash)
VCCf
tVCS
tVACCR tVLHT
VID VIH WP/ACC CEf
WE
tVLHT tVLHT
RY/BY
Acceleration Mode Period
32
MB84VD23381EF-85
* Extended Sector Group Protection (Flash)
VCCf
tVCS
RESET
tVIDR
tVLHT tWC tWC
Address
SPAX
SPAX
SPAY
A0
A1
A6
CEf
OE
TIME - OUT tWP
WE
Data
60h
60h
40h tOE
01h
60h
SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 s (Min)
33
MB84VD23381EF-85
* READ Cycle (FCRAM) Parameter Read Cycle Time Address Setup Time at CE1s High to Low Transition Address Hold Time during CE1s Low Address Access Time Chip Enable Access Time Output Enable Access Time Output Data Hold Time CE1s Low to Output Low-Z OE Low to Output Low-Z CE1s High to Output High-Z OE High to Output High-Z CE1s High Pulse Width CE1s High to Address Hold Time Address Invalid Time during Read (CE1s = Low) Symbol tRC tASC tAHC tAA tCE tOE tOH tCLZ tOLZ tCHZ tOHZ tCP tCHAH tAX Value Min 90 -5 90 5 10 0 10 -5 Max 1000 85 85 60 25 15 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns *5 *2 *3 *3 *3 *3 *4 *4 *4 *4
Remarks
*1
*1 : Maximum value is a reference and is applied to Output Disable condition. *2 : tAHC must be satisfied every address valid state after tAX during CE1s = Low. *3 : Output load is 30 pF. *4 : Output load is 5 pF. *5 : If actual address change before CE1s High transition is earlier than tCHAH (min) , tCP (CE1s High period) should be kept at least tRC (min) period.
34
MB84VD23381EF-85
* READ Timing 1 (CE1s Control) (FCRAM)
tRC tRC Address Valid tAHC tCHAH tASC tCE tCHAH
Address
tASC
Address Valid tAHC tCE
CE1s
tCP * tOE tCHZ tOHZ
OE
tOH tOLZ tCLZ tOH
DQ (Output)
Valid Data Output Valid Data Output
Note : CE2s and WE must be HIGH for entire read cycle. * : Output Disable condition before new Read data valid should not be kept longer than 1 s.
* READ Timing 2 (Address Access) (FCRAM)
tRC
tAX
tRC Address Valid tAHC tAA
tAX
Address
tCHAH tASC
Address Valid tAHC tCE
CE1s
tCP * tOE *
OE
tOHZ tOLZ tOH tOH
DQ (Output)
Valid Data Output Valid Data Output
Note : CE2s and WE must be HIGH for entire read cycle. * : Output Disable condition before new Read data valid should not be kept longer than 1 s.
35
MB84VD23381EF-85
* WRITE Cycle (FCRAM) Parameter Write Cycle Time Address Setup Time Address Hold Time CE1s Write Setup Time CE1s Write Hold Time WE, LBs, UBs Setup Time WE, LBs, UBs Hold Time OE Setup Time OE Hold Time OE High to CE1s Low Setup Time OE High to Address Hold Time CE1s Write Pulse Width WE Write Pulse Width CE1s Write Recovery Time WE Write Recovery Time Data Setup Time Data Hold Time CE1s Low to Output in Low-Z OE Low to Output in Low-Z Symbol tWC tAS tAH tCS tCH tBS tBH tOES tOEH tOHCL tOHAH tCW tWP tWRC tWR tDS tDH tCLZ tOLZ Value Min 90 0 40 0 0 0 0 0 15 -5 0 60 60 15 15 20 10 10 0 Max 1000 1000 1000 1000 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *8 *8 *3 *4 *5, *6 *5, *6 *7 *2, *7 *2 *2 Remarks *1
*1 : Maximum value is a reference and applied to Output Disable condition. *2 : Maximum value is applied to Output Disable condition. *3 : tOHCL (min) must be satisfied if read operation is not performed prior to write operation. In case OE is disabled after tOHCL (min), WE Low must be asserted after tRC (min) from CE1s Low. *4 : Applicable if CE1s stays Low after read operation. *5 : tWHP (max) must be satisfied for the high pulse noise. *6 : tCW and tWP are applied if write operation is initiated by CE1s and WE, respectively. *7 : tWRC and tWR are applied if write pulse is terminated by CE1s and WE, respectively. *8 : Output load is 5 pF.
36
MB84VD23381EF-85
* WRITE Timing 1 (CE1s Control) (FCRAM)
Address
tAS
Address Valid tAH tWC
CE1s
tBS tCW tWRC tBH
WE
tBS
tBH
UBs, LBs
tOHCL
tOEH
OE
tDS tDH tCLZ
DQ (Input)
Valid Data Input
Note : CE2s must be HIGH during the write cycle.
37
MB84VD23381EF-85
* WRITE Timing 2 (WE Control) (FCRAM)
Address
tOHAH tAS
Address Valid tAH tCH
CE1s
tOHCL tCS tWC
WE
tWP tBS tWR tBH
UBs, LBs
tOES
tOEH
OE
tOHZ tDS tDH tOLZ
DQ (Input)
Valid Data Input
Note : CE2s must be HIGH during the write cycle.
38
MB84VD23381EF-85
* BYTE WRITE Timing 1 (CE1s Control) (FCRAM)
Address
tAS
Address Valid tAH tWC
CE1s
tBS tCW tWRC tBH
WE
tBS
tBH
UBs, LBs
tOHCL
tOEH
OE
tDS tDH tCLZ
DQ (Input)
Valid Data Input
Note : CE2s must be HIGH and either LBs or UBs must be LOW during byte write cycle.
39
MB84VD23381EF-85
* BYTE WRITE Timing 2 (WE Control) (FCRAM)
Address
tOHAH tAS
Address Valid tAH tCH
CE1s
tOHCL tCS tWC
WE
tWP tBS tWR tBH
UBs, LBs
tOES
tOEH
OE
tOHZ tDS tDH tOLZ
DQ (Input)
Valid Data Input
Note : CE2s must be HIGH and either LBs or UBs must be LOW during the byte write cycle.
40
MB84VD23381EF-85
* READ/WRITE Timing 1-1 (CE1s Control) (FCRAM)
Address
tAS tCHAH
Address Valid tAH tWC
Don't Care tASC
CE1s
tCP tBS tCW tBH tWRC tBS
WE
tBS tBH
UBs, LBs
tOHCL tOEH
OE
tCHZ tDS tDH tCLZ
DQ
Read Data Output Write Data Input
Note : Write address is edge trigger of either CE1s or WE falling edge.
41
MB84VD23381EF-85
* READ/WRITE Timing 1-2 (CE1s Control) (FCRAM)
Address
tASC
Read Address Valid tAHC tCHAH tAS
Write Address
CE1s
tWRC tBH tBS tCP tRC tBS
WE
tBH tBS
UBs, LBs
tOEH tCE tOE tOHCL
OE
tOLZ tDH tCLZ tOH tCHZ
DQ
Wrire Data Input Read Data Output
Note : WE must be HIGH during the read cycle.
42
MB84VD23381EF-85
* READ/WRITE Timing 2-1 (OE and WE Control) (FCRAM)
tAX
Address
tOHAH tAS
Address Valid tAH
Don't Care
CE1s
tWC Low tWP tWR
WE
tBS tBH
UBs, LBs
tOES tOEH
OE
tOHZ tDS tDH tOLZ
DQ
Read Data Output Write Data Input
Note : CE1s can be tied to LOW for WE and OE controlled operation. When CE1s is tied to LOW, output is exclusively controlled by OE and read address can be issued after WE is brought to High. WARNING : The read address following write operation must be changed if CE1s stays LOW.
43
MB84VD23381EF-85
* READ / WRITE Timing 2-2 (OE and WE Control) (FCRAM)
tAX
Address
Read Address Valid tAHC tOHAH tAS
Write Address
CE1s
Low tWR tRC
WE
tBH tAA tBS
UBs, LBs
tOEH tOE tOES
OE
tOHZ tDH tOLZ tOH
DQ
Write Data Input Read Data Output
44
MB84VD23381EF-85
* POWER DOWN PARAMETER (FCRAM) Parameter CE2s Low Setup Time for Power Down Entry CE1s Low Pulse Width during Power Down Mode CE2s Low Hold Time after Power Down Exit (CE1s = High) CE1s High Hold Time following CE2s High after Power Down Exit *1 : Requires at least two dummy read cycles. *2 : Required when dummy read cycles are not performed. * OTHER TIMING PARAMETER (FCRAM) Parameter CE1s High to OE Invalid Time for Standby Entry CE1s High to WE Invalid Time for Standby Entry CE1s and CE2s Active Glitch Pulse Width CE1s or WE High Glitch Pulse Width during Write Cycle CE2s Low Hold Time after Power-up CE1s High Hold Time following CE2s High after Power-up *1 : Active means a condition where CE1s = VIL and CE2s = VIH. *2 : Specified to the one time high pulse width during tCW or tWP and excluded 10 ns from beginning and end of the write cycle. *3 : Requires at least two dummy read cycles. *4 : Required when dummy read cycles are not performed. Symbol tCHOX tCHWX tCAP tWHP tC2LP tC1HP Value Min 10 20 350 300 Max 5 5 Unit ns ns ns ns s s *1 *2 *3 *4 Note Symbol tCSP tCPP tC2LP tC1HP Value Min 100 100 350 300 Max Unit ns ns s s *1 *2 Note
45
MB84VD23381EF-85
* Standby Entry Timing after Read or Write (FCRAM)
CE1s
tCHOX tCHWX
OE
WE
Active (Read) Standby Active (Write) Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (min) period from either last address transition or CE1s Low to High transition. * Chip Enable Timing (FCRAM)
CE1s
tCAP
tCAP
tCAP
CE2s
Note : tCAP is not applicable CE2s HIGH pulse width while CE1s stays LOW and CE2s should not use as a read and write timing control signal in stead of CE1s. * POWER DOWN Timing (FCRAM)
tCPP
CE1s
tCSP tC2LP
CE2s
Power Down Entry
Power Down Mode
Power Down Exit
Note : A minimum of two dummy read cycle must be performed prior to regular read and write operation after tC2LP . Otherwise CE1s must kept High for tC1HP period after tC2LP .
46
MB84VD23381EF-85
* Power-Up Timing 1 (FCRAM)
*1
tRC*2
tRC
CE1s
tAHC tC2LP tCP tAHC tCP
CE2s
VCCs
0V
VCCs min.
*1 : It is recommended CE1s to track VCCs. The tC2LP specifies from valid state of CE1s = High and CE2s = Low after VCCs reaches specified minimum level. *2 : 2A minimum of two dummy read cycle must be performed prior to regular read and write operation after tC2LP . * Power-Up Timing 2 (No dummy cycle) (FCRAM)
*1
tC1HP*2
CE1s
tC2LP
CE2s
VCCs
0V
VCCs min.
*1 : It is recommended CE1s to track VCCs. The tC2LP specifies from valid state of CE1s = High and CE2s = Low after VCCs reaches specified minimum level. *2 : No dummy read cycle is required if tC1HP is satisfied.
47
MB84VD23381EF-85
s ERASE AND PROGRAMMING PERFORMANCE (FLASH)
Parameter Sector Erase Time Word Programming Time Chip Programming Time Erase/Program Cycle Limits Min 100,000 Typ 1 16 Max 10 360 200 Unit s s s cycle Comments Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead
s PACKAGE PIN CAPACITANCE
Parameter Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance Symbol CIN COUT CIN2 CIN3 Test Setup VIN = 0 V VOUT = 0 V VIN = 0 V VIN = 0 V Value Typ 11 12 14 21.5 Max 14 16 16 26 Unit pF pF pF pF
Note : Test conditions TA = +25 C, f = 1.0 MHz
s HANDLING OF PACKAGE
Please handle this package carefully since the sides of package are created with acute angles.
s CAUTION
* The high voltage (VID) cannot be applied to address pins and control pins except RESET. Exception is when autoselect and Sector Group Protection function are used. Then the high voltage (VID) can be applied to RESET. * Without the high voltage (VID) , Sector Group Protection can be achieved by using "Extended Sector Group Protection" command.
48
MB84VD23381EF-85
s ORDERING INFORMATION
MB84VD23381
EF
-85
PBS
PACKAGE TYPE PBS = 101-ball FBGA SPEED OPTION
Device Revision
DEVICE NUMBER/DESCRIPTION 64 Mega-bit (4 M x 16-bit) Dual Operation Flash Memory 3.0 V-only Read, Program, and Erase 16 Mega-bit (1 M x 16-bit) FCRAM
49
MB84VD23381EF-85
s PACKAGE DIMENSION
101-ball plastic FBGA (BGA-101P-M01)
12.000.10(.472.004) 0.20(.008) S A
+.006 (Seated height) .047 -.004 0.390.10 (Stand off) (.015.004)
1.19 -0.10
+0.15
B 0.40(.016) REF 0.80(.031) REF 12 11 10 9 8 7 6 5 4 3 2 1 PNMLK JHGFEDCBA
0.80(.031) REF A 11.000.10 (.433.004) 0.40(.016) REF 0.10(.004) S
INDEX-MARK AREA 0.20(.008) S A
S
101-O0.45 -0.05 101-O.018 -.002
+0.10 +.004
0.08(.003)
M
SAB
0.10(.004) S
C
2001 FUJITSU LIMITED B101001S-c-3-3
Dimensions in mm (inches)
50
MB84VD23381EF-85
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0204 (c) FUJITSU LIMITED Printed in Japan

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